Product Overview - Details
The entire design hierarchy is held in memory - this allows complex edits to be seamlessly applied across entire hierarchical connections with a single action. Applying type definitions, changing signal widths, re-naming signals , setting work libraries, removing signals etc no longer involves locating and editing a myriad of source files.
Keeping the entire design in memory allows a smooth transfer of design information both up and down the hierarchy. A signal is typed in once, from then on the signal is moved from level-to-level, block-to-block by a simple mouse click (or drag). You won't have to perform some arcane 'link' to hook each hierarchical level together and then resolve name or width mismatches at the block boundaries.
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Automatic hierarchy documentation
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Simple click of a button produces accurate, readable hardcopy documentation which is guaranteed to be up to date- sizes from A4 to plotters (A0). US paper sizes are also fully catered for. The drawing border, on screen, matches the physical paper size. Drawings are automatically scaled to fit the chosen paper size. A2 drawings are readable at A4 print sizes as long as the printer has a resolution equal to or greater than 600DPI.
Both hardcopy and HDL source can be stamped with user supplied information (version, date/time, etc) to allow easy identification of equivalent data.
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Full support for complex type systems
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Full support, via the Types Designer, for the underlying HDL type system. Any built-in or user defined type is fully supported. For instance, in VHDL, there is full support for ACCESS, ARRAY, RECORD, INT etc.
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Unique compound Interface objects
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Simplest way to think of Interface objects is as a named bundle of multiple signals. They simplify routing and maintenance - instances are routed as a named entity using a single graphical line, any edits to the elements are applied to all instances of the object. Useful for describing standard (PCI, SCSI, etc), proprietary buses or just for routing convenience. Interface objects use compound object support provided by the target HDL (records in VHDL) or can be flattened during code generation using automatic name uniquification.
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Advanced net based drawing methodology
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Signal information is shown on the graphical connection rather than repeated on the pins at each end point. This novel approach allows multiple signals to be added to a single graphical line significantly reducing the number of graphical connections that need to be drawn and ultimately maintained.
Designs are less congested and thus far more readable. Less time is spent 'tidying up'. Signal relationships can be captured improving the transfer and preservation of design knowledge and intent.
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Scalable from small to very large designs
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Expressive has been successfully used on designs ranging from 30k to over 3m gates. The graphical techniques have been developed to provide a truly scaleable environment, yet at the same time offer real benefits to designers engaged in smaller designs.
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Multiple data views simplifies visualization of complex data
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Depending on the task at hand, design data can be formatted and presented in ways which are most convenient. Adding comments to signals is easiest when the signal name pool for a block is presented in table format. The Data Dictionary provides a fast and convenient mechanism. The Hierarchy View shows the entire design in a single, interactive tree view. The Unused/Unconnected dialog shows unconnected signals in a convenient table format. There are a number of other data views such as the Browser, Generics/Parameters Editor, the Work Library editor etc. The Explorer allows direct navigation to any level within the design, skipping intermediate levels as required. Access to all primary editing functions is fully supported. Design object searching is provided using UNIX style wildcards.
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Custom integration of text editors, HDL compilers,
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Using the built in wizard, external tools can be identified to Expressive. These can take the form of simple processes, such as editors, HDL compilers, report generators, etc or can involve multi-step operations. Tools are integrated using a combination of fixed text and 'just-in-time' macros. As the command is applied to a design unit, these macros are expanded out using data provided by the design unit. This way commands can be described once and used anywhere. Output from commands is displayed in a transcript window, which is linked into the search engine for added convenience.
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Flexible wildcard searching tools
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The powerful search system fully supports UNIX style C-Shell wildcards. This is very useful when trying to locate incompletely specified objects
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Unique code generation options
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Adopting a port based mechanism for passing signals through hierarchical boundaries (as opposed to pins) provides some very useful data organization options for code generation. The general mechanism for boundary IO and wire signals is to separate them by direction and then sort each group alphanumerically. Ports provide a unique mechanism by allowing signals to be grouped in the HDL source code by port. Each port grouping is still sorted by direction, alphanumerically. As port objects support the notion of a comment, this comment can be passed through to the HDL code right above its signal group.
Not only can you comment each signal individually, but can now add a comment to a group of signals.
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Textual languages to describe behavior
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You use the HDL (VHDL or Verilog) of choice to describe functional behavior - so there's no new language or syntax to learn. All your accumulated knowledge on constructing code for synthesis is fully preserved. The hierarchy is entered graphically, but the implementation is done in text. Your control over what synthesis sees is fully preserved - you write the code so you have the control.
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Unique ability to record abstract data relationships
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The use of ports to transfer signals between hierarchical levels allows signals which are functionally related to be collected together and associated with a meaningful comment. Multiple signals sharing the same connection can be used in this way. Nets can optionally be marked as containing signals grouped as either address, data or control - significantly improves design readability.
Multi-bit signals can be created with non-zero starting indexes. Bits can be extracted/merged by simple reference using indexes. Sub-ranges can be extracted/merged by simple range indexes. The multi-level editing options allow signals to be quickly refined - you don't need to know the final width of a signal before it can be added to the design. This flexibility allows you to capture your thoughts and ideas well before the full details are available .
Testbench templates can be created for any level within the design hierarchy. Two styles of template is available - one where the UUT is instantiated inline with the testbench code, the other style constructs a top level testbench that instantiates both the UUT and the testbench block. All of the UUT instantiation and interconnect signals are automatically maintained as the design changes.
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Flexible, language independent script processor
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The Script Processor takes a file or files, written in any language (perl, tcl, do, C++, VHDL, Verilog etc) and expands any embedded macros to real values and passes non-macro text straight through unchanged. Macros provide access to data supplied from a block with in the design or general design data such as that contained in the design information area of the drawing sheet.
The Script Processor is run with the code generator, so your scripts are kept up to date automatically. This system is typically used to maintain the scripts for simulation and synthesis, but can be used for any purpose.
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